Joint Optimization of Data Path and Memory Hierarchy for Deep Learning Accelerator Architectures

Abstract

This paper investigates the architectural design of deep learning accelerator chips, with a focus on addressing the challenge of inefficient coordination between the data path and memory hierarchy in traditional chip architectures when processing deep learning tasks. Deep learning algorithms are characterized by substantial computational demands and complex data access patterns, which impose stringent requirements on both computing performance and storage capacity. To address these challenges, a coordinated optimization model is developed based on the intrinsic characteristics of deep learning algorithms. In data path design, systolic array structures are adopted to optimize matrix operation pathways and enhance the efficiency of computing units. In the memory hierarchy, performance improvements are achieved through optimized cache strategies and the integration of high-bandwidth memory technologies, thereby enhancing data storage and access performance.